As is known in the art, many Monolithic Microwave Integrated Circuit (MMIC) structures use Coplanar Waveguide (CPW) to interconnect various electrical devices and elements of the circuit. The CPW has both the strip conductor and the adjacent ground plane conductors on the same side of a substrate where the electrical devices and elements of the circuit are formed. These ground plane conductors provide the local ground plane for the circuit. The backside of the MMIC substrates provided with a metal, such as thick electro-plated gold, to enable a thermal conductive bond between the metal and an underlying heat sink structure and also serves as an RF signal ground for the MMIC. When fed with an RF source, the RF source is connected between the strip conductor and the backside metal. The local ground planes (i.e., the CPW ground planes, sometimes referred to herein as local ground plane conductors or local grounds) are electrically connected to the backside signal ground.
As is also known in the art, Silicon Carbide (SiC) has typically been used for substrates with Gallium Nitride (GaN) MMICs. These (SiC) substrates typically have a thickness of about 500 microns. However, the use of diamond substrates has been more recently considered. These diamond substrates are inherently thinner with thickness of typically 100 microns or less.
In the case where substrate vias are not used such as with Silicon Carbide (SiC) or diamond, the space for connection between the CPW local ground and the backside signal ground is limited and sometimes the connections may be available only at the edges of the chip. Thus, there may be a physical connection between the local ground and the signal ground at only a few locations such as the RF input and output of the chip, and the DC bias and power supply connections. With such limitation, the local ground on the substrate front-side and the signal ground plane on the backside of the chip form an electrical network that supports parallel plate mode propagation. The parallel plate mode generates unwanted resonances and other deleterious electromagnetic coupling effects that affect electrical performance of the MMIC. The degree to which circuit performance is impacted depends on the thickness of the substrate and other factors such as overall chip dimensions relative to wavelength. MMICs with thinner substrates are more strongly affected as the proximity of the backside metallization favors more coupling between the CPW mode and the parallel plate mode. Whereas CPW MMICs on 500 um thick SiC substrates are only moderately affected by the backside metallization, the effect is much stronger with the thinner substrates such as 100 um thick diamond. The impact of the thinner substrate on CPW tuning must be taken into account.
Some of the prior work with CPW tuning simply neglects the impact of the backside ground due to the electrically thick SiC substrate. In other cases, effects brought about by the backside metallization such as parallel plate mode resonances, are dealt with after the fact by adding mode suppression resistors using a cut and trial procedure. Others try to moderate the impact of the backside ground metallization during the design by restricting the size of a CPW transmission line so that the widths and gaps are less than ⅓ of the substrate height. This practice can be adequate for thick 500 um substrates, but it is impractical for 100 um thick substrates because it imposes too many restrictions on the range of dimensions available for design. The corresponding lines would be too narrow and add significant loss to a CPW tuning network, degrading MMIC performance. There is published research that documents the impact of the backside ground on CPW lines with a thin substrate; see for example “Transmission Characteristics of Finite-Width Conductor-Backed Coplanar Waveguide” by Ching-Cheng Tien et al, IEEE Transactions on Microwave Theory and Techniques, vol. 41, No. 9, pp. 1616-1624, September 1993.
As is also known in the art, during the design of a MMIC, computer simulations are made to iteratively evaluate the design. One simulation software is called “Advanced Design System (ADS)” from Agilent Technologies. As is known, the software includes a library of active and passive electrical elements including transmission lines (i.e., electrical components). In such library, a typical CPW transmission line component is modeled as a two-port (i.e., input port and output port) device and the local ground planes are referenced to the RF signal ground potential; however, with such model there is no simulation of the effect of the parallel plate referred to above.
A conventional port setup for analyzing CPW circuits consist of a single port on the center conductor and an implicitly defined pair of topside current return ports. By definition the sum of the return currents is equal in magnitude and opposite in the direction of flow to the current in the center conductor. This arrangement is sometimes referred to as a push-pull port configuration. This zero-sum solution neglects any additional currents that are associated with the backside ground plane. Another common CPW approach consists of connecting the local topside CPW ground conductors to a perfectly conducting box serving as ground reference and surrounding the circuit model. This approach imposes a particular boundary condition on the fields and resulting currents, i.e. the conducing box, which in general is different than the actual environment of the circuit. In the latter case the solution of the analysis is specific to the particular configuration and generally not suitable for design purposes. Thus neither approach is capable of representing the currents of conductor backed CPW circuits accurately.